View UPD161830P_487292.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

PRELIMINARY PRODUCT INFORMARTION
MOS INTEGRATED CIRCUIT
PD161830
240-OUTPUT TFT-LCD SOURCE DRIVER (COMPATIBLE WITH 64-GRAY SCALES)
DESCRIPTION
The PD161830 is a source driver for TFT-LCDs supporting 64 gray-scale display and can operate with a supply voltage of 2.5 V for the logic block and 5.0 V for the driver block. Data input as 6-bit x 3-dot digital data is output as 64 -corrected values using an internal D/A converter and 5 external power modules, thus achieving a 260,000-color (full-color) display.
FEATURES
* CMOS level input * 240 outputs * Input of 6 bits (gray-scale data) by 3 dots * Capable of outputting 64 values by means of 5 external power modules and a D/A converter * Output dynamic range: VSS2 to VDD2 * High-speed data transfer: fCLK = 15 MHz MAX. (internal data transfer speed when operating at VDD1 = 2.5 V) * Level inversion -correction power supply is possible * Logic power supply voltage (VDD1): 2.2 to 3.6 V * Driver power supply voltage (VDD2): 4.5 to 5.5 V
ORDERING INFORMATION
Part Number Package Chip
PD161830P
Remark Purchasing the above chip entail the exchange of documents such as a separate memorandum or product quality, so please contact one of our sales representatives.
The information contained in this document is being issued in advance of the production cycle for the device. The parameters for the device may change before final production or NEC Corporation, at its own discretion, may withdraw the device prior to its production. Not all devices/types available in every country. Please check with local NEC representative for availability and additional information.
Document No. S16240EJ2V0PM00 (2nd edition) Date Published July 2002 NS CP (K) Printed in Japan
The mark # shows major revised points.
(c)
2002
PD161830
1. BLOCK DIAGRAM
STHL VDD1(2.5 V) VSS1 C79 C80
STHR R,/L CLK INV D00 to D05 D10 to D15 D20 to D25 C1 C2
80-bit bidirectional shift register
INBUF
Data register
CM STB POL Mode control
AP MODE VCsel VCOM
Latch
VCOM BUF
Level shifter
VDD2 (5.0 V) VSS2
V0 to V4
GAM VDD1 TESTIN TESTO1 TESTO2
BA
control
D/A converter
BIAS control
Output buffer
S1
S2
S3
S240
Remark
/xxx indicates active low signal.
2
Preliminary Product Information S16240EJ2V0PM
PD161830
2. PIN CONFIGURATION (Pad Layout)
Chip size: 15.84 x 1.11 mm
2 2
Bump size (Input/VCOM/test/dummy): 80 x 86 m Bump size (Output): 29 x 103 m Alignment Mark (m) X: 7716.45 Y: 347.04 X: -7716.45 Y: 347.04
2
1 241 242 Y X 246 247 326 327 332 331
Alignment mark shape (unit: m)
29.04 29.04 89.52
89.52
Preliminary Product Information S16240EJ1V0PM
3
PD161830
Table 2-1. Pad Layout (1/2)
No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 Name S1 S2 S3 S4 S5 S6 S7 S8 S9 S10 S11 S12 S13 S14 S15 S16 S17 S18 S19 S20 S21 S22 S23 S24 S25 S26 S27 S28 S29 S30 S31 S32 S33 S34 S35 S36 S37 S38 S39 S40 S41 S42 S43 S44 S45 S46 S47 S48 S49 S50 S51 S52 S53 S54 S55 S56 S57 S58 S59 S60 X [ m] 7170.000 7110.000 7050.000 6990.000 6930.000 6870.000 6810.000 6750.000 6690.000 6630.000 6570.000 6510.000 6450.000 6390.000 6330.000 6270.000 6210.000 6150.000 6090.000 6030.000 5970.000 5910.000 5850.000 5790.000 5730.000 5670.000 5610.000 5550.000 5490.000 5430.000 5370.000 5310.000 5250.000 5190.000 5130.000 5070.000 5010.000 4950.000 4890.000 4830.000 4770.000 4710.000 4650.000 4590.000 4530.000 4470.000 4410.000 4350.000 4290.000 4230.000 4170.000 4110.000 4050.000 3990.000 3930.000 3870.000 3810.000 3750.000 3690.000 3630.000 Y [ m] 396.480 396.480 396.480 396.480 396.480 396.480 396.480 396.480 396.480 396.480 396.480 396.480 396.480 396.480 396.480 396.480 396.480 396.480 396.480 396.480 396.480 396.480 396.480 396.480 396.480 396.480 396.480 396.480 396.480 396.480 396.480 396.480 396.480 396.480 396.480 396.480 396.480 396.480 396.480 396.480 396.480 396.480 396.480 396.480 396.480 396.480 396.480 396.480 396.480 396.480 396.480 396.480 396.480 396.480 396.480 396.480 396.480 396.480 396.480 396.480 No. 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 Name S61 S62 S63 S64 S65 S66 S67 S68 S69 S70 S71 S72 S73 S74 S75 S76 S77 S78 S79 S80 S81 S82 S83 S84 S85 S86 S87 S88 S89 S90 S91 S92 S93 S94 S95 S96 S97 S98 S99 S100 S101 S102 S103 S104 S105 S106 S107 S108 S109 S110 S111 S112 S113 S114 S115 S116 S117 S118 S119 S120 X [ m] 3570.000 3510.000 3450.000 3390.000 3330.000 3270.000 3210.000 3150.000 3090.000 3030.000 2970.000 2910.000 2850.000 2790.000 2730.000 2670.000 2610.000 2550.000 2490.000 2430.000 2370.000 2310.000 2250.000 2190.000 2130.000 2070.000 2010.000 1950.000 1890.000 1830.000 1770.000 1710.000 1650.000 1590.000 1530.000 1470.000 1410.000 1350.000 1290.000 1230.000 1170.000 1110.000 1050.000 990.000 930.000 870.000 810.000 750.000 690.000 630.000 570.000 510.000 450.000 390.000 330.000 270.000 210.000 150.000 90.000 30.000 Y [ m] 396.480 396.480 396.480 396.480 396.480 396.480 396.480 396.480 396.480 396.480 396.480 396.480 396.480 396.480 396.480 396.480 396.480 396.480 396.480 396.480 396.480 396.480 396.480 396.480 396.480 396.480 396.480 396.480 396.480 396.480 396.480 396.480 396.480 396.480 396.480 396.480 396.480 396.480 396.480 396.480 396.480 396.480 396.480 396.480 396.480 396.480 396.480 396.480 396.480 396.480 396.480 396.480 396.480 396.480 396.480 396.480 396.480 396.480 396.480 396.480 No. 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 Name S121 S122 S123 S124 S125 S126 S127 S128 S129 S130 S131 S132 S133 S134 S135 S136 S137 S138 S139 S140 S141 S142 S143 S144 S145 S146 S147 S148 S149 S150 S151 S152 S153 S154 S155 S156 S157 S158 S159 S160 S161 S162 S163 S164 S165 S166 S167 S168 S169 S170 S171 S172 S173 S174 S175 S176 S177 S178 S179 S180 X [ m] -30.000 -90.000 -150.000 -210.000 -270.000 -330.000 -390.000 -450.000 -510.000 -570.000 -630.000 -690.000 -750.000 -810.000 -870.000 -930.000 -990.000 -1050.000 -1110.000 -1170.000 -1230.000 -1290.000 -1350.000 -1410.000 -1470.000 -1530.000 -1590.000 -1650.000 -1710.000 -1770.000 -1830.000 -1890.000 -1950.000 -2010.000 -2070.000 -2130.000 -2190.000 -2250.000 -2310.000 -2370.000 -2430.000 -2490.000 -2550.000 -2610.000 -2670.000 -2730.000 -2790.000 -2850.000 -2910.000 -2970.000 -3030.000 -3090.000 -3150.000 -3210.000 -3270.000 -3330.000 -3390.000 -3450.000 -3510.000 -3570.000 Y [ m] 396.480 396.480 396.480 396.480 396.480 396.480 396.480 396.480 396.480 396.480 396.480 396.480 396.480 396.480 396.480 396.480 396.480 396.480 396.480 396.480 396.480 396.480 396.480 396.480 396.480 396.480 396.480 396.480 396.480 396.480 396.480 396.480 396.480 396.480 396.480 396.480 396.480 396.480 396.480 396.480 396.480 396.480 396.480 396.480 396.480 396.480 396.480 396.480 396.480 396.480 396.480 396.480 396.480 396.480 396.480 396.480 396.480 396.480 396.480 396.480
4
Preliminary Product Information S16240EJ2V0PM
PD161830
Table 2-1. Pad Layout (2/2)
No. 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 201 202 203 204 205 206 207 208 209 210 211 212 213 214 215 216 217 218 219 220 221 222 223 224 225 226 227 228 229 230 231 232 233 234 235 236 237 238 239 240 Name S181 S182 S183 S184 S185 S186 S187 S188 S189 S190 S191 S192 S193 S194 S195 S196 S197 S198 S199 S200 S201 S202 S203 S204 S205 S206 S207 S208 S209 S210 S211 S212 S213 S214 S215 S216 S217 S218 S219 S220 S221 S222 S223 S224 S225 S226 S227 S228 S229 S230 S231 S232 S233 S234 S235 S236 S237 S238 S239 S240 X [ m] -3630.000 -3690.000 -3750.000 -3810.000 -3870.000 -3930.000 -3990.000 -4050.000 -4110.000 -4170.000 -4230.000 -4290.000 -4350.000 -4410.000 -4470.000 -4530.000 -4590.000 -4650.000 -4710.000 -4770.000 -4830.000 -4890.000 -4950.000 -5010.000 -5070.000 -5130.000 -5190.000 -5250.000 -5310.000 -5370.000 -5430.000 -5490.000 -5550.000 -5610.000 -5670.000 -5730.000 -5790.000 -5850.000 -5910.000 -5970.000 -6030.000 -6090.000 -6150.000 -6210.000 -6270.000 -6330.000 -6390.000 -6450.000 -6510.000 -6570.000 -6630.000 -6690.000 -6750.000 -6810.000 -6870.000 -6930.000 -6990.000 -7050.000 -7110.000 -7170.000 Y [ m] 396.480 396.480 396.480 396.480 396.480 396.480 396.480 396.480 396.480 396.480 396.480 396.480 396.480 396.480 396.480 396.480 396.480 396.480 396.480 396.480 396.480 396.480 396.480 396.480 396.480 396.480 396.480 396.480 396.480 396.480 396.480 396.480 396.480 396.480 396.480 396.480 396.480 396.480 396.480 396.480 396.480 396.480 396.480 396.480 396.480 396.480 396.480 396.480 396.480 396.480 396.480 396.480 396.480 396.480 396.480 396.480 396.480 396.480 396.480 396.480 No. 241 242 243 244 245 246 247 248 249 250 251 252 253 254 255 256 257 258 259 260 261 262 263 264 265 266 267 268 269 270 271 272 273 274 275 276 277 278 279 280 281 282 283 284 285 286 287 288 289 290 291 292 293 294 295 296 297 298 299 300 Name DUMMY1 DUMMY2 DUMMY3 DUMMY4 DUMMY5 DUMMY6 DUMMY7 VCOM STHL DUMMY8 VDD2 VDD2 VDD2 VDD1 VDD1 VDD1 VSS1 VSS1 VSS1 VSS2 VSS2 VSS2 VCSEL R,/L MODE BA GAM CM POL AP STB D25 D24 D23 D22 D21 D20 CLK DUMMY9 V4 V4 V4 V3 V3 V3 V2 V2 V2 V1 V1 V1 V0 V0 V0 DUMMY10 INV D15 D14 D13 D12 X [ m] -7311.420 -7772.010 -7772.010 -7772.010 -7772.010 -7772.010 -7654.530 -7479.510 -7229.490 -7054.440 -6793.050 -6693.090 -6593.130 -6331.710 -6231.750 -6131.790 -5878.440 -5778.480 -5678.520 -5428.500 -5328.540 -5228.580 -4975.260 -4725.240 -4475.220 -4225.200 -3975.180 -3725.160 -3475.140 -3225.120 -2975.100 -2725.080 -2475.060 -2225.040 -1975.020 -1725.000 -1474.980 -1224.960 -1049.910 -874.860 -774.900 -674.940 -424.920 -324.960 -225.000 25.080 125.040 225.000 475.020 574.980 674.940 925.020 1024.980 1124.940 1299.990 1475.010 1725.030 1975.050 2225.070 2475.090 Y [ m] 407.010 164.880 64.860 -35.160 -135.180 -235.200 -407.010 -407.010 -407.010 -407.010 -407.010 -407.010 -407.010 -407.010 -407.010 -407.010 -407.010 -407.010 -407.010 -407.010 -407.010 -407.010 -407.010 -407.010 -407.010 -407.010 -407.010 -407.010 -407.010 -407.010 -407.010 -407.010 -407.010 -407.010 -407.010 -407.010 -407.010 -407.010 -407.010 -407.010 -407.010 -407.010 -407.010 -407.010 -407.010 -407.010 -407.010 -407.010 -407.010 -407.010 -407.010 -407.010 -407.010 -407.010 -407.010 -407.010 -407.010 -407.010 -407.010 -407.010 No. 301 302 303 304 305 306 307 308 309 310 311 312 313 314 315 316 317 318 319 320 321 322 323 324 325 326 327 328 329 330 331 332 Name D11 D10 D05 D04 D03 D02 D01 D00 TESTO1 TESTO2 TESTIN VDD1 VDD1 VDD1 VSS1 VSS1 VSS1 VSS2 VSS2 VSS2 VDD2 VDD2 VDD2 DUMMY11 STHR DUMMY12 DUMMY13 DUMMY14 DUMMY15 DUMMY16 DUMMY17 DUMMY18 X [ m] 2725.110 2975.130 3225.150 3475.170 3725.190 3975.210 4225.230 4475.250 4725.270 4975.290 5225.310 5475.360 5575.320 5675.280 5853.630 5953.590 6053.550 6303.570 6403.530 6503.490 6843.180 6943.140 7043.100 7304.490 7479.540 7654.560 7772.010 7772.010 7772.010 7772.010 7772.010 7311.420 Y [ m] -407.010 -407.010 -407.010 -407.010 -407.010 -407.010 -407.010 -407.010 -407.010 -407.010 -407.010 -407.010 -407.010 -407.010 -407.010 -407.010 -407.010 -407.010 -407.010 -407.010 -407.010 -407.010 -407.010 -407.010 -407.010 -407.010 -235.200 -135.180 -35.160 64.860 164.880 407.010
Preliminary Product Information S16240EJ1V0PM
5
PD161830
3. PIN FUNCTIONS
(1/2)
Pin Symbol S1 to S240 D00 to D05 D10 to D15 D20 to D25 R,/L Shift direction control input Pin Name Driver output Display data input Pad No. I/O Input Description The display data is input with a width of 18 bits, viz., the gray scale data (6 bits) by 3 dots (1 pixels). DX0: LSB, DX5: MSB These refer to the shift direction control input. The shift directions of the shift registers are as follows. R,/L = L (left shift): STHL (input), S240 S1 STHR (output) R,/L = H (right shift) : STHR (input), S1 S240 STHL (output) These refer to the start pulse I/O pins when driver ICs are connected in cascade. Fetching of display data starts when H is read at the rising edge of CLK. R,/L = L (left shift): STHL input, STHR output R,/L = H (right shift): STHR input, STHL output This pin is the shift clock input of the shift register. Display data is captured into the data register at the rising edge. The start pulse output enters high level at the rising edge of the 80 th clock following the start pulse input, and becomes the start pulse of the next level driver. The 81th clock of the first driver becomes the start pulse input of the next driver A timing signal that latches the contents of the data register. When an H level is read at the rising edge of CLK, the contents of the data register are latched and transferred to the D/A converter, and analog voltage corresponding to the display data is output. Also, because the internal operation via CLK continues even after the STB latch, do not stop CLK. The contents of the shift register are cleared at the rising edge of STB. Following a 1-pulse input at startup, this IC will operate normally. Note that the output switch is turned off at the rising edge of STB. For the STB input timing, refer to Switching Characteristics Waveform. This pin inverts the output polarity. The polarity inversion signal data is captured at the rising edge of STB. The -resistor is switched in accordance with the positive/negative polarity. POL = L: Negative polarity POL = H: Positive polarity This pin inverts the input data. Input data in synchronization with the shift clock. INV = L: Normal input INV = H: Data inversion input 1 to 240 Output The D/A converted 64-gray-scale analog voltage is output.
308 to 303 302 to 297 277 to 272
264
Input
STHR STHL CLK
Right shift start 325 pulse input/output Left shift start 249 pulse input/output Shift clock input 278
I/O I/O Input
STB
Latch input
271
Input
POL
Polarity inversion signal
269
Input
INV
Data inversion
296
Input
VCOM
COM amplitude output
248
Output This pin inverts the signal input from the POL pin and outputs it following conversion to the VDD2 potential at the rising edge of STB. When the VCOM output is not used, VCsel must be fixed to L. Input The VCOM output is fixed to L. When the VCOM output is not used, VCsel needs to be fixed to L. VCsel = L: VCOM output fixed to L VCsel = H: VCOM signal output in correspondence with POL signal The operating mode is switched to 8-color mode. Input data MSB leads display data. In this mode, turn off the -resistor, amplifier, and BIAS circuit. However, when the correction power supply is input externally, the -circuit current will flow continuously. CM = L: Normal display mode CM = H: 8-color display mode
VCsel
COM amplitude 263 output fixing signal
CM
8-color display mode switching
268
Input
6
Preliminary Product Information S16240EJ2V0PM
PD161830
(2/2)
Pin Symbol AP Pin Name Output SW ON/OFF Pad No. 270 I/O Input Description MODE = L This pin turns ON/OFF the BIAS circuit and turns on the output SW and amplifier. When AP is H, the amplifier is set and the LCD is driving. The amplifier output and output SW are turned on at the rising edge of AP, starting the LCD drive. Note that the output SW is turned off at the rising edge of STB and the output becomes Hi-Z (Hi-Z: High impedance). For details, refer to 4.1 Drive Timing by MODE and AP Signal. For the AP input timing, refer to Switching Characteristics Waveform. MODE = H A sauce driver output circuit is changed to an amplifier output by grand fixation. For details, refer to 4.1 Drive Timing by MODE and AP Signal. GAM External -usage selection 267 Input When the -correction power supply is input externally, switch GAM to H. If two or more chips are used, be sure to input the -correction power supply externally. Figure 4-4 shows an input example of the -correction power supply. GAM = L: External -correction power supply not input (open) GAM = H: External -correction power supply input The drive mode of the sauce driver output by AP pin is set up as follows. For details, please refer to 4.1 Drive Timing by MODE and AP Signal. MODE = L: Normal drive mode MODE = H: Grand output drive mode V0 to V4
MODE
Driver output 265 functional change
Input
-corrected power 294 to 280 supplies
-
These pins input the -corrected power supplies from outside, the relationship below must be observed. Also, be sure to stabilize the gray-scale-level power supply during gray-scale voltage output. VSS2 V4 V3 V2 V1 V0 VDD2 This pin adjusts the BIAS current and through rate of amplifier inside IC. Select either the high power mode or low power mode. In addition, as compared with the time of the low power mode, twice about as many bias current as this flows at the time of high power mode. BA = L: Low power mode BA = H: high power mode Set to H or leave open
BA
BIAS current adjustment function
266
Input
TESTIN TESTO1, TESTO2 VDD1 VDD2 VSS1 VSS2
TEST input pin TEST output pin Logic power supply Driver power supply Logic ground Driver ground
311 309, 310 254 to 256, 312 to 314 251 to 253, 321 to 323 257 to 259, 315 to 317 260 to 262, 318 to 320
241 to 247, 250, 279, 295, 324, 326 to 332
Input
Output Leave open. - - - - - 2.2 to 3.6 V 4.5 to 5.5 V Ground Ground This pin is dummy.
Dummy1 to Dummy dummy18
Caution
To avoid latchup failure, the sequence when turning on the power must be VDD1 logic input VDD2 gray-scale power supply (V0 to V4), and the reverse sequence when turning off the power. Follow this sequence during shift periods as well.
Preliminary Product Information S16240EJ1V0PM
7
PD161830
4. DISPLAY DRIVING CIRCUIT
The display driving circuit of PD161830 consists of -resistance and -selection switch (SW) which are shown below, a D/A converter, and an output stage. The function of each block is as follows.
-resistance
D/A converter Output stage
: It is string resistance for -curve. : Choose an output voltage level from display data. : It consists of amplifier for a drive and a switch for a voltage maintenance drive, and an inverter for 8 color displays. Figure 4-1. Output Circuit Image
-selection switch (SW): Change -curve at the time of a positive and a negative drive.
V0
-selection SW Positive Negative
DAC SW OUT
AMP
Output for 8-color display
V10
8
Preliminary Product Information S16240EJ2V0PM
PD161830
4.1 Drive Timing by MODE and AP Signal *MODE = L Normal drive is selected when a MODE pin is set as L. Based on output stage construction, AP pin, STB pin, CLK pin signal, and the relation of Sn (sauce output) state are shown in the next figure. From 1 clock of a CLK signal to 4 clock is used for the output stage after a STB standup, it carries out decoding to the latch output voltage level of display data, and transmits to an output circuit. The output circuit's having prevented from Sn pin output compulsorily the output of the level which is not decided as a Hi-Z state from the standup of a STB signal to the standup of a CLK signal 4 clock. When AP pin is L input after 4 clock rises, as for Sn pin output, Hi-Z state is maintained, and an output circuit changes from the standup of AP pin input to an AMP drive state. Moreover, Sn pin outputs that the notes 1 which pull up to the voltage (display data) level which requires the potential of a TFT drain line, or are reduced requirement voltage level L, output circuit stage operation is changed into SW drive level. Since liquid crystal load is driven only by SW drive of -resistance direct file when referred to as AP = L before attainment of the level to demand, most time is needed for level attainment. Since this timing (AP = H period) is dependent on the load conditions of liquid crystal, it is a real use TFT panel and fully needs to be evaluated. Notes 1. When it is always set as AP = H, Sn pin starts an AMP drive automatically after the standup of 4 clock. 2. At the time of SW drive, stop the bias current of an output stage amplifier circuit, and stop the consumption current of the output stage.
Note2 Note1
.
When low power consumption is required, AMP pin is switched from H to L, after a voltage level attain to , and it stabilizes a voltage
Preliminary Product Information S16240EJ1V0PM
9
PD161830
Figure 4-2. Output Stage Operation Image
V0
selection SW + DAC SW OUT
AMP
Hi-Z state
OFF
AMP drive
OFF
SW drive
ON
OFF AMP V10 AMP
ON AMP
OFF
Hi-Z state
AMP drive
SW drive
AP
STB
CLK
4 CLK
Hi-Z minimum period
Sn
10
Preliminary Product Information S16240EJ2V0PM
PD161830
Examples of the input/output timing of each signal during white and black display in normal mode are shown below. Figure 4-3. Timing Chart
STB
AP POL
DATA
DATA = 000000
DATA = 111111
VCOM
260,000-color display mode (CM = L)
Hi-Z
Hi-Z
Hi-Z
Hi-Z
OUT
Undefined
Black level
Black level
White level
White level
8-color display mode
OUT
Black level
LSB MSB
Black level
White level
White level
MSB used in 8-color display mode
Preliminary Product Information S16240EJ1V0PM
11
PD161830
*MODE = H (GND output driving) When a MODE pin is set as H, the output change function by AP pin is changed as follows.
AP Pin L H
Sn Pin (source output) Drive GND output (VSS fixed) Normal AMP operation
As for sauce output, output is fixed to ground (VSS) in falling of AP signal at the time of GND output drive (MODE = H). Moreover, the return to an APM drive usually returns from the next STB = H period which latched AP = H by the rising edge of STB signal. The relationship of the CLK signal at the time of a GND output drive, a STB signal, AP signal, and Sn state is shown as follows.
STH CLK STB AP Latch AP = H MODE "H" SAMPLING POL Data S1 to S240
ALL = 0
Hi-Z AMP driving
SAMPLING DATA
SAMPLING DATA
SAMPLING DATA
GND
Hi-Z
AMP driving
The next STB = H output start which latched AP = H.
12
Preliminary Product Information S16240EJ2V0PM
PD161830
4.2 -Correction Power Supply Connection Example The PD161830 enables customization of the -correction power supply on both the positive and negative polarity sides (refer to 6. RELATIONSHIP BETWEEN INPUT DATA AND OUTPUT VOLTAGE VALUE). Consequently, a correction power supply does not have to be input externally when a single source-driver chip is being used in the panel. Multiple chips can also be used without having to input a -correction power supply externally because the error between the chips can be absorbed by shorting the -correction power supply pins, as shown in Figure 4-4. Figure 4-4. -Correction Power-Supply Connection Example
*Single chip
Open
External power supply input
VDD2 VSS2
V0 V1 V2 V3 V4
VSS2 VDD2
External power supply input
External power supply input
VDD2 VSS2
V0 V1 V2 V3 V4
VSS2 VDD2
*Multiple chips
Vn - Vn short
External power supply input
VDD2 VSS2
V0 V1 V2 V3 V4
VSS2 VDD2
VDD2 VSS2
V0 V1 V2 V3 V4
VSS2 VDD2
External power supply input
External power supply input
VDD2 VSS2
V0 V1 V2 V3 V4
VSS2 VDD2
VDD2 VSS2
V0 V1 V2 V3 V4
VSS2 VDD2
Preliminary Product Information S16240EJ1V0PM
13
PD161830
4.3 CLK Signal Input Input at least 4 clocks of the CLK signal after the rising of the STB signal.
STB
1 2 3 4 /1 2 3 4 5 6 7 8
CLK STH
5
Drive timing
Internal latch signal1 Note Internal latch signal2 Note Internal latch signal3 Note
Invalid
D1 to D3
D4 to D6
D7 to D9 D10 to D12 D13 to D15 D16 to D18 D19 to D21
Note Internal latch signal : It is the signal that do latch the display data put in data register in output latch circuit.
5. MODE EXPLANATION
Normal Mode/ 8-clor Display Mode
CM H H POL MSB = H MSB = L L MSB = H MSB = L L H All bit = H All bit = L L All bit = H All bit = L 260,000-color mode Data Driver Output Status 8-color mode Driver Output (in normally white) White level display Black level display White level display Black level display White level display Black level display White level display Black level display
14
Preliminary Product Information S16240EJ2V0PM
PD161830
6. RELATIONSHIP BETWEEN INPUT DATA AND OUTPUT VOLTAGE VALUE
The relationship between input data and output voltage are shown in Table 6-2. Any 3 major points V1 to V3 from the LCD panel -characteristics curve can be used as the external power supplies. The relationship V0 to V4 external power supplies and -correction resistance is shown in Table 6-1, Figure 6-1. Table 6-1. Relationship between External Power Supply Pins and -correction Resistance
Pin Name V0 V1 V2 V3 V4 Voltage (V) 5.0 3.5 2.5 1.5 0 Resistance () 0 7,500 12,500 17,500 25,000
Figure 6-1. Relationship between External Power Supply Pins and -correction Resistance
VDD2
V0
7500
V1
5000
V2
5000
V3
7500
V4
VSS2
This external power supply pins (V0 to V4) can customize the -correction voltage by selecting the desired voltage from one of 250 divisions of the string resistor between VSS2 and VDD2, which generated -correction voltage. Note that the voltage can be selected individually for both positive and negative polarity.
Preliminary Product Information S16240EJ1V0PM
15
PD161830
Table 6-2. Relationship of Input Data and Output Voltage in the PD161830 - T.B.D. Remark T.B.D. (To be determined.)
16
Preliminary Product Information S16240EJ2V0PM
PD161830
6.1 Connection between -correction Resistance, Power Supply, and GND Pin Connection of - compensation resistance power supply (V0 to V4) and a power supply pin (VDD2 and VSS2) is indicated below to be - compensation resistance of PD161830. By setup of a GAM pin, as for -compensation resistance, connection changes the highest minimum potential between VDD2 to VSS2 or among V0 to V4. Figure 6-2. GAM Pin Function -
VDD2 SW1 V0
GAM
-selectionSW Positive Negative polarity polarity
GAM = L
SW1
SW2 V1
V2
GAM = H
V3 SW1
SW2 V4 SW2
GAM
VSS2
Preliminary Product Information S16240EJ1V0PM
17
PD161830
7. RELATIONSHIP BETWEEN INPUT DATA AND OUTPUT PIN
Data format: 6 bits x RGBs (3 dots) Input width: 18 bits (1-pixel data) R,/L = H (Right shift)
Output Data S1 D00 to D05 S2 D10 to D15 S3 D20 to D25 S4 D00 to D05 ... ... S239 D10 to D15 S240 D20 to D25
R,/L = L (Left shift)
Output Data S1 D00 to D05 S2 D10 to D15 S3 D20 to D25 S4 D00 to D05 ... ... S239 D10 to D15 S240 D20 to D25
18
Preliminary Product Information S16240EJ2V0PM
PD161830
8. ELECTRICAL SPECIFICATIONS
Absolute Maximum Ratings (TA = 25C, VSS1 = VSS2 = 0 V)
Parameter Logic Part Supply Voltage Driver Part Supply Voltage Input Voltage Output Voltage Operating Ambient Temperature Storage Temperature Symbol VDD1 VDD2 VI VO TA Tstg Rating -0.3 to +4.5 -0.3 to +6.0 -0.3 to VDD1,2 + 0.3 -0.3 to VDD1,2 + 0.3 -20 to +75 -55 to +125 Unit V V V V C C
Caution Product quality may suffer if the absolute maximum rating is exceeded even momentarily for any parameter. That is, the absolute maximum ratings are rated values at which the product is on the verge of suffering physical damage, and therefore the product must be used under conditions that ensure that the absolute maximum ratings are not exceeded.
Recommended Operating Range (TA = -20 to +75C, VSS1 = VSS2 = 0 V)
Parameter Logic Part Supply Voltage Driver Part Supply Voltage High-Level Input Voltage Low-Level Input Voltage Symbol VDD1 VDD2 VIH VIL V0 to V4 fCLK Condition MIN. 2.2 4.5 0.7 VDD1 0 VSS2 5.0 TYP. MAX. 3.6 5.5 VDD1 0.3 VDD1 VDD2 15 Unit V V V V V MHz
-Corrected Voltage
Clock Frequency
Preliminary Product Information S16240EJ1V0PM
19
PD161830
Electrical Characteristics (TA = -20 to +75C, VDD1 = 2.2 to 3.6 V, VDD2 = 5.0 V 0.5 V, VSS1 = VSS2 = 0 V)
Parameter Input Leak Current Symbol IIL Condition D00-D05, D10-D15, D20-D25, R,/L, STB, CLK, STHR(L), INV, CM, AP, BA, POL, GAM, VCsel Input Current High-Level Output Voltage Low-Level Output Voltage VCOM Output Voltage IIL2 VOH VOL VOH2 VOL2 TESTIN STHR (STHL), IOH = -1.0 mA STHR (STHL), IOL = +1.0 mA VDD2 = 5.0 V, IO = -1.0 mA VDD2 = 5.0 V, IO = +1.0 mA V0 = 5.0 V, V4 = 0 V (when in -correction power mode) IVOH1 IVOL1 Driver Output Current (Switch drive) IVOL2 Driver Output Current (8-color display mode) Output Voltage Deviation Output Voltage Range Consumption Driver Part Dynamic Current Consumption IDD2 VDD = 5.0 V, with no load
Note2
MIN.
TYP.
MAX. 1.0
Unit
A
10 VDD1 - 0.5
40
200 0.5
A
V V V V
VDD2 - 0.5 0.5 100 200 400
-Correction Power-supply I
Static Current Consumption Driver Output Current (AMP drive)
A
VDD2 = 5.0 V, VOUT = VX - 1.0 V Input data: 1FH VDD2 = 5.0 V, VOUT = VX + 1.0 V Input data: 20H VDD2 = 5.0 V, VOUT = VX - 1.0 V Input data: 1FH VDD2 = 5.0 V, VOUT = VX + 1.0 V Input data: 20H VDD2 = 5.0 V, IO = -50 A VDD2 = 5.0 V, IO = +50 A VDD1 = 2.5 V, VDD2 = 5.0 V, VOUT = 2.5 V
Note1
Note1
-0.5 0.15 0.50 -50 15 VDD2 - 0.5 40
-0.15
mA mA
Note1
IVOH2
Note1
-15
A A
V
Note1
VVOH3 VVOL3 VO VO
0.5 10 VSS2 + 0.05 0.4 0.9 20 VDD2 - 0.05 0.8 1.5
V mV V mA mA
Input data: 00H to 3FH With no load
Note2
Logic Part Dynamic Current IDD1
Notes 1. VX refers to the output voltage of analog output pins S1 to S240. VOUT refers to the voltage applied to analog output pins S1 to S240. 2. fCLK = 15 MHz, STB cycle = 60 s, AP pulse width = 15 s, BA=L (low power mode)
20
Preliminary Product Information S16240EJ2V0PM
PD161830
Switching Characteristics (TA = -20 to +75C, VDD1 = 2.2 to 3.6 V, VDD2 = 5.0 V 0.5 V, VSS1 = VSS2 = 0 V)
Parameter Start Pulse Delay Time Symbol tPLH1 tPHL1 Driver Output Delay Time (High power mode) Driver Output Delay Time (Low power mode) Input Capacitance tPLH2H tPHL2H tPLH2L tPHL2L CI1 CI2 CL = 30 pF AP VOUT - 100 mV or VOUT + 100 mV CL = 30 pF AP VOUT - 100 mV or VOUT + 100 mV V0 to V4, TA = 25C Excluded V0 to V4, TA = 25C 5 10 CL = 15 pF Condition MIN. TYP. MAX. 25 25 12 12 15 15 15 15 Unit ns ns
s s s s
pF pF
Timing Requirements (TA = -20 to +75C, VDD1 = 2.2 to 3.6 V, VSS1 = 0 V, tr = tf = 10 ns)
Parameter Clock Pulse Width Clock Pulse High Period Clock Pulse Low Period Data Setup Time Data Hold Time Start Pulse Setup Time Start Pulse Hold Time Start Pulse Low Period Last Data Timing CLK-STB Time STB Pulse Width Start Pulse Rising Time INV Set-up Time INV Hold Time STB Set-up Time STB Hold Time POL-STB Time STB-POL Time CM-STB Time STB-CM Time STB-AP Time AP Pulse Width (High power mode) AP Pulse Width (Low power mode) AP Set-up Time AP Hold Time Symbol PWCLK PWCLK(H) PWCLK(L) tSETUP1 tHOLD1 tSETUP2 tHOLD2 tSPL tLDT tCLK-STB PWSTB tSTB-STH tSETUP3 tHOLD3 tSETUP4 tHOLD4 tPOL-STB tSTB-POL tCM-STB tSTB-CM tSTB-AP PWAPH PWAPL tSETUP5 tHOLD5 STB cycle 40s, CL = 30 pF STB, MODE = H STB, MODE = H STB AP STB STH CLK STB Condition MIN. 65 20 20 20 20 20 20 3 2 20 40 3 20 20 20 20 0 40 0 40 20 12 15 0 40 TYP. MAX. Unit ns ns ns ns ns ns ns CLK CLK ns ns CLK ns ns ns ns ns ns ns ns
s s s
ns ns
Preliminary Product Information S16240EJ1V0PM
21
5 Switching Characteristic Waveform (R,/L= H)
22
PWCLK CLK PWCLK(L) 1 tSETUP2 tHOLD2 tSPL STHR (1st Dr.) tSETUP1 DATA INVALID D1 to D3 tHOLD1
Last Data
Unless otherwise specified, the input level is defined to be VIH = 0.7 VDD1, VIL = 0.3 VDD1.
PWCLK(H) 2 3 80 81 90%
tr
tf
10%
D4 to D6 tPLH1 tPHL1
INVALID
Preliminary Product Information S16240EJ2V0PM
STHL (1st Dr.)
tLDT
tSETUP4
tHOLD4
PWSTB
tCLK-STB STB
tSTB-STH
tSETUP3 tHOLD3
INV tPOL-STB tSTB-POL POL tCM-STB tSTB-CM CM tSTB-AP PWAB AP
tPLH2
VOUT
Hi-Z
Hi-Z tPHL2
PD161830
PD161830
NOTES FOR CMOS DEVICES
1 PRECAUTION AGAINST ESD FOR SEMICONDUCTORS Note: Strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and ultimately degrade the device operation. Steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it once, when it has occurred. Environmental control must be adequate. When it is dry, humidifier should be used. It is recommended to avoid using insulators that easily build static electricity. Semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. All test and measurement tools including work bench and floor should be grounded. The operator should be grounded using wrist strap. Semiconductor devices must not be touched with bare hands. Similar precautions need to be taken for PW boards with semiconductor devices on it. 2 HANDLING OF UNUSED INPUT PINS FOR CMOS Note: No connection for CMOS device inputs can be cause of malfunction. If no connection is provided to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence causing malfunction. CMOS devices behave differently than Bipolar or NMOS devices. Input levels of CMOS devices must be fixed high or low by using a pull-up or pull-down circuitry. Each unused pin should be connected to VDD or GND with a resistor, if it is considered to have a possibility of being an output pin. All handling related to the unused pins must be judged device by device and related specifications governing the devices. 3 STATUS BEFORE INITIALIZATION OF MOS DEVICES Note: Power-on does not necessarily define initial status of MOS device. Production process of MOS does not define the initial operation status of the device. Immediately after the power source is turned ON, the devices with reset function have not yet been initialized. Hence, power-on does not guarantee out-pin levels, I/O settings or contents of registers. Device is not initialized until the reset signal is received. Reset operation must be executed immediately after power-on for devices having reset function.
Preliminary Product Information S16240EJ1V0PM
23

▲Up To Search▲

Price & Availability of UPD161830P

	To Download UPD161830P Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .